As part of the annual 'Hot Chips' convention, Oracle have released a couple of details about the hot-ly anticipated M7 incarnation of the SPARC CPU line up. Featuring 8 core clusters, and a total of 32 cores per socket the SPARC M7 has 10 Billion, yes BILLION transistors on one chip.

Up 12 cores on the M6, the M7 is on a 20nm process - allowing for very small transistors.

Oracle SPARC M7 Processor

L3 Cache is shared across the cores in 8 x 8MB partitions, offering a total of 64 MB per chip. In total, bandwidth for the L3 cache is over 1.6 TB/s. The core clusters share the L2 cache, with 4 cores in each cluster sharing 256 KB of L2 Instruction Set - offering over half a TB/s of throughput.

Scalability of the SPARC M7 is offered via 7 coherence links per chip, which allows up to 8 M7's to be connected together seamlessly. Further scaling can be done via SMP, offering a potential 1024 cores, 8192 threads and up to 64 TB of RAM.

Oracle also report that the M7 has the ability to uncompress data at the same speed as memory access, working directly with compressed data IN the memory. This should offer performance increases to database functions. These won't be limited to those running Oracle Database, but will be fully transparent to those that are.

We expect an official arrival of the SPARC M7 in 2015, with official clock speed ratings to be released in the near future. With the M6 currently clocked at 3.6 GHz, even a small increase in clock speed will make the SPARC M7 cpu capable of a great many things.

One of which includes the 'real time application data integrity' - which checks data in memory for errors, from software bugs or exploits. Usually this is saved for debug or dev, but the M7 will perform quickly enough to do this with your live apps.

Memory capacity per socket will be upped to 2TB across 16 memory channels, with DDR4 offering between 12.8 and 16 GB/sec bandwidth. Supported memory speeds will include 2.1 GHz, 2.4 GHz, and 2.67 GHz - using the 2.1 GHz memory, a single socket will offer 160 GB/sec of memory bandwidth. This is 2X the speed of the T5, and 3X of M6.

Four PCI-e 3.0 links per M7 will support 75 GB/sec of bandwidth - again 2X more than the T5 and M6 chips.

The SPARC M7 will the power the next generation of T and M series Oracle servers, full details of which are yet to be confirmed!

Talk to your BSI account manager about SPARC appliances, applications, or for any Oracle based query you may have.