Last week (28/08/2013), Oracle unveiled details of the SPARC M6 cpu, with IBM in its crosshairs. Reaction is positive from those with memory hungry compute needs. Scalable to 96 sockets, the SPARC M6 should hold the attention of large corporations and governmental institutions.

At the centre of the SPARC M6 lies the S3 core, as per the T4, T5, and M5. Not flexing the muscle of big clock speeds, but the M6 should have applications where S3 is at home. 

The SPARC M6 will be on a 28nm process, featuring 12 Cores and 96 Threads, a 48MB Level 3 cache with up to 1TB of memory per socket - 2 Gen 3.0 PCIe controllers will also be on board. The M6 is the same 28nm process as the M5, but the physical chip is larger with twice the number of cores.

The S3 core has an out of order pipeline, that's dual issue - appearing as 8 threads as opposed to one to OS - thank to Sun Microsystems simultaneous multithreading. These 'dynamic pipelines' as they're known - can hold resources for as long as they require them if they have the priority.

Oracle SPARC M6 Processor

With regards to caching on the chip, L1 has 16KB, and L2 has 128KB - which is a little low by modern standards. Even though the shared Level 3 has 48 MB across all cores. Looking to the future, the M6 scalability would max out at 9,216 threads in a single system - thanks to the extended bixby interconnect. The M6 chip has four memory controllers, each one feeding a buffer chip, with each of those having two memory channels. This equates to 16 total channels and 32 physical DIMM slots - which support 32GB DIMMs - giving the M6 scalability to 96 TB for those that need it.

With seven scalability links and seven coherence links (SL/CL) the SPARC M6 is capable of a lightning fast 4.1 Tb/sec of bandwidth. The 12 cores on the chip are linked by a 12-by-5 crossbar interconnect with four of the pipes connecting the cores to each of the four 12MB L3 cache segments.

One thing we were particularly interested in is that the M5 and M6 will ship simultaneously - and will be able to run side-by-side in the same system - allowing for gradual upgrade. Something that IBM and Intel do not allow with their hardware.

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